The present invention generally relates to semiconductor wafer testing apparatus and, more particularly, to a closed loop temperature sensing feedback system using an area-selected temperature controlled wafer chuck.
In previous practice, when wafer testing undiced semiconductor chip devices and circuitry at the then prevailing relatively low chip wattage levels (well below the 20 watt range), the required chip junction temperature of about 25 degrees Centigrade was readily maintainable. More recently, however, it has become necessary to test chip devices in undiced wafer form at wattage levels of 20 watts and beyond. Unless the thermal resistance of the wafer-chuck interface is maintained below about 1.2 degrees Centigrade per watt, it becomes very difficult, if not impossible, to obtain reliable functional test results while maintaining chip junction temperature at about 25 degrees Centigrade. Known available chuck temperature control techniques do not lend themselves to the high wattage testing of individual chips of an uncut wafer.
High wattage chips heat up significantly during wafer final test. The electrical performance of the chip depends on its operating or "junction" temperature. Performance degrades with increasing junction temperature in a non-linear manner. A certain minimum performance level is required of every chip to pass final test. In establishing this level, it had been assumed that the junction temperature held constant during test at the value prescribed in the test specification. This assumption worked reasonably well in the past, when the power levels of the chips were low (less than 5 watts.) Higher power levels make the assumption erroneous. When testing high wattage chips, there is a significant difference between the prescribed test temperature and the actual junction temperature. For example, at 20 watts of chip power, the chip can be an average of 50 degrees centigrade hotter than the chuck, the device used to support the wafer and control its temperature during final test. Worse yet, the variability of this temperature rise makes it difficult to predict the actual junction temperature, given the power input and the chuck temperature. In the example given, the junction can actually be anywhere between 25 degrees Centigrade and 75 degrees Centigrade hotter than the thermochuck. The product yield is directly affected by this uncertainty, since good chips could be testing as bad chips due simply to overheating.
The ideal approach is to actually measure the junction temperature of the device as it is being tested, and use it as a feedback control signal to the chuck temperature control system. Provided enough cooling power is available, this method would maintain the junction temperature within a narrow range centered at the prescribed temperature. Unfortunately, such a direct approach is not yet feasible in practice, and it is unlikely to become a reality in the near future. Temperature sensitive diodes would have to be placed in the chip to provide the temperature feedback, but their outputs would not be easily accessible or measurable.
The principle of operation of the state of the art in wafer temperature control is to keep constant the temperature of the chuck which supports the wafer, by means of a closed loop temperature feedback control system. The temperature of the chuck is monitored by a thermocouple and cooling power is provided by respective thermoelectric elements mounted under the plate. The control unit turns the thermoelectric element on and off as required to keep the thermocouple within 2 degrees Centrigrade of the prescribed temperature. However, extensive studies have shown that with this set-up, the only useful and statistically valid junction temperature prediction that can be made is that chips dissipating under 25 watts would remain under 85 degrees Centigrade when tested on a 10 degree Centigrade chuck.
IBM (R) Technical Disclosure Bulletin, Vol. 31, No. 1, June 1988, "Electrostatic Wafer Holder for Wafer Cooling During Reactive Ion Etching" by G. Fortune and J. H. Keller discloses one technique useful in lowering the thermal resistance at the wafer-chuck (wafer-holder) interface in a reactive ion etching application. The wafer is electrostatically clamped to its holder while helium gas is applied to the backside of the wafer through annular surface grooves in the holder. However, the cited publication does not address the problem of cooling solely an area portion or domain of a wafer which is non-uniformly heated, wherein only a small surface of the wafer is heated at one time as caused by the testing of only one chip at a time among many others comprising the surface of a common undiced wafer.
Helium gas also is used in channels on the face of a wafer chuck for providing thermal contact to the back of a wafer which is mounted on the chuck as described in European patent publication 0250064, published Dec. 23, 1987, Bulletin 87/52 by George L. Coad et al. The wafer is tightly secured to the chuck by holding clamps to reduce helium leak. Again, there is no teaching of heating or cooling a wafer whose temperature is non-uniform across the face of the wafer.